Switched capacitor amplifiers are compatible with CMOS technology and consequently are therefore frequently used as analog building blocks in CMOS circuits. In general, the design methodology in CMOS amplifiers assumes the use of infinite gain and infinite bandwidth operational amplifiers. However, CMOS amplifiers have a relatively low gain because of the low gain inherent in CMOS devices. The maximum gain of a CMOS switched amplifier, i.e., open circuit gain, is approximately 25, and may be as low as 10. The low gain of CMOS switched amplifiers introduce finite gain error when the gain of the amplifier is assumed to be the ratio of the capacitance of an input capacitance to the capacitance of a feedback capacitor.
FIG. 1 shows a switched capacitor amplifier 100 having an input capacitor 104 having a capacitance of Cin connected to an inverting input 116 of an operational amplifier 112, which is assumed to have infinite gain. The amplifier 100 also includes a feedback capacitor 108 having a capacitance of Cfb coupled in series with an NMOS switching transistor 110 between an output 124 of the amplifier 112 and the inverting input 116. The feedback capacitor 108 forms a closed loop via the transistor 110 to provide feedback from an output terminal 124 of the operational amplifier 112 to the inverting input terminal 116. A non-inverting input 120 of the operational amplifier is connected to the ground. As a matter of convention, it should be understood that the terms “non-inverting input” terminal and “inverting input” terminal are used with respect to their relationship to a particular output terminal. An amplifier could alternatively be considered to have an “inverting output” terminal and a “non-inverting output” terminal, as one skilled in the art will appreciate. For example, rather than refer to an amplifier as having an inverting input terminal and an output terminal, one could refer to the same amplifier as having an input terminal and an inverting output terminal.
Another switched NMOS transistor 126 is connected between the input capacitor 104 and an input voltage source 128. The gates of the transistors 110, 126 both receive a Q1 switching signal so they are both ON at the same time. When the transistors 110, 126 are turned ON, the input voltage source 128 is applied to the input capacitor 104. As a result, the input capacitor 104 is charged since the input terminal 116 is a virtual ground because of the feedback through the capacitor 108. The capacitor 108 is also charged for that same reason. The capacitor 108 is charged to a voltage Vout that is equal to the product of the voltage −Vin and ratio of the capacitance of the input capacitor 104 to the capacitance of the feedback capacitor 108.
A switched NMOS transistor 136 is connected between the input capacitor 104 and the ground, another NMOS transistor 138 is connected between the feedback capacitor 108 and ground, and another NMOS transistor 140 is connected between the output terminal 124 and the inverting input 116. When the transistors 136, 138, 140 are ON responsive to a high Q2 signal applied to their gates, the capacitors 104, 108 are discharged to the ground, and the output terminal 124 is reset to zero volts.
In operation, the Q1 and Q2 signals are alternately driven to a high logic level. Therefore, the transistors 110, 126 are operated in a complementary manner with the transistors 136, 138, 140 thereby causing the capacitors 104, 108 to be alternately charged and discharged. Periodically discharging the capacitors 104, 108 prevents offsets that would otherwise be present at the output terminal 124 of the amplifier 100.
In the discussion of the amplifier 100 shown in FIG. 1, it was assumed that the open-loop gain of the operational amplifier 112 was infinite. However, a typical CMOS differential amplifier does not have an open-loop gain that even approaches infinity. With an operation amplifier 112 having a more limited open-loop gain, the approximate closed loop gain of the operational amplifier is given by the following equation:Vout/Vin=−Av/[((1+Cfb*(Av+1))/Cin)]  (1)where Av is the open-loop gain of the operational amplifier.If Av is very large, equation (1) can be approximated as follows:Vo/Vin=−Cin/Cfb  (2)
Thus, as explained above with respect to the amplifier 112 used in the amplifier 100 of FIG. 1, if the open-loop gain Av is very large, the closed-loop gain of the amplifier is approximately equal to the ratio of the capacitance Cin of the input capacitor 104 to the capacitance Cfb of the feedback capacitor 108. However, since CMOS amplifiers invariably do not have high open-loop gain, equation (2) does not provide an accurate result.
Suppose for example, Av=100 and Cin/Cfb=10. If Av is very large, equation (2) can be used, and Vo/Vin=−10. However, if Av is 10, then, equation (1) provides Vo/Vin =−9. The simplified formula, i.e., equation (2), based on the ratio of the capacitances predicts a gain of 10, but the actual gain from a more accurate analysis using equation (1) predicts a gain of 9. The error, which is the difference in gain, is caused by the low open-loop gain of the CMOS amplifier. If the open-loop gain of the CMOS amplifier could be increased, the error could be eliminated, and the closed-loop gain of the amplifier would be simply the ratio of the input capacitance Cin to the feedback capacitance Cfb given by equation (2). Since the capacitance of capacitors can be controlled fairly precisely during manufacture, the gain of a switched capacitance amplifier could then be precisely controlled.
Another technique for dealing with the relatively low open-loop gain of CMOS amplifiers is to factor the open-loop gain of the CMOS amplifier into the closed-loop gain using equation (1) to provide the desired level of gain. However, it is fairly impractical to fabricate a CMOS amplifier with a precisely controlled open-loop gain since the gain can vary with process variations. The open-loop gain of a CMOS amplifier can also change with temperature or supply voltage variations. Without a stable value for the open-loop gain of a CMOS amplifier, it is not possibly to use equation (1) to calculate a precise closed-loop gain for a switched capacitor amplifier.
There are also other approaches that can be used for attempting to provide switched capacitance CMOS amplifiers with stable gain characteristics. However, all of these approaches impose limitations or costs on switched capacitance CMOS amplifiers using these approaches. For example, some approaches result in the use of greatly increased surface area on a die, and other approaches provided somewhat limited performance.
Accordingly, there is a need for a CMOS amplifier circuit having very high open-loop gain so that the closed-loop gain of a switched capacitor amplifier can be precisely controlled and does not vary with process, supply voltage and temperature variations.